The present invention relates to electronic circuits, and more particularly, to loop circuits.
A phase-locked loop (PLL) is an electronic circuit that generates one or more periodic (clock) output signals. A PLL adjusts the frequency of a feedback signal from the output of an oscillator to match in phase the frequency of an input reference clock signal. Phase-locked loops (PLLs) are an essential building block of many integrated circuits, providing periodic signals for data recovery, data transfer, and other clocking functions.
A delay-locked loop (DLL) is another electronic circuit that generates one or more output clock signals. A DLL adjusts the phase of a feedback signal to match the phase of an input reference clock signal. Clock signals generated by PLLs and DLLs are often distributed through an integrated circuit or electronic system.